Verifying correct operation of digital logic circuits at their expected clock rate (e.g., speed) remains an important activity for semiconductor manufacturers when testing semiconductor devices. Defects that cause digital logic circuits to malfunction at expected clock rates are modeled as delay faults. Delay faults cause errors in the functioning of the digital logic circuits based on timing. They are typically caused by increases in finite rise and fall times of electrical signals at Boolean gates of semiconductor elements and propagation delay of interconnects between the gates. In a general sense, at-speed behavior of digital logic circuits is emulated to detect and characterize such delay faults. One of several fault models that have been proposed for emulating and testing delay faults is the transition fault model. The transition fault model assumes that gate delays and interconnect delays on all paths passing through a particular site manifest themselves as a gross delay at that site, called a fault site. Hence, sensitizing any path that passes through the fault site is enough to detect the fault. Today, scan-based testing techniques using the transition fault model are increasingly used to test for delay faults.